The invention is related to a circuit and method for providing synchronous clock signals having respective programmable frequency ratios with respect to a master clock signal frequency.
Systems providing two or more synchronous clock signals having different frequencies are known to utilize a master clock signal generator and respective frequency dividers, each providing a desired frequency division ratio with respect to the master clock signal frequency. A synchronization signal which is necessary to synchronize the various frequency dividers is known to be obtained from an external source. Synchronous clock signals are useful for example in various digital signal transmission systems, in digital data processing systems such as utilizing two or more synchronized serial-to-parallel or parallel-to-serial data converters and in similar applications. The known prior art systems have a disadvantage that when the frequency ratio of one or more clock signals is changed it is necessary to change accordingly the synchronization signal frequency and thus to replace the respective frequency dividers and other circuit components to adapt the circuit to the changed frequency ratio.